Integrated injection logic (I.sup.2 L) circuits are now well established in the art and widely publicized in the technical literature. Attention is drawn for example to articles in the IEE Journal of Solid-State Circuits, Vol SC-7, No 5 Oct 1972, at page 340 and page 346. The I.sup.2 L concept is essentially based on inverting single or multiple collector transistors which are powered by direct minority carrier injection close to their emitter-base junctions (order or magnitude, one diffusion length). This bipolar logic concept has very short switching times. In addition it is suitable for the manufacture of extremely highly integrated large-scale logical circuits.
Numerous patents and publications disclose I.sup.2 L circuitry. Reference is made to the following U.S. Pat. Nos.: 3,736,477 entitled "Monolithic Semiconductor Circuit For A Logic Circuit Concept of High Packing Density" granted May 29, 1973 to H. H. Berger and S. K. Wiedmann; 3,956,641 entitled "Complementary Transistor Circuit for Carrying Out Boolean Functions" granted May 11, 1976 to H. H. Berger et al; and, 4,330,853 entitled "Method of and Circuit Arrangement For Reading And/Or Writing an Integrated Semiconductor Storage With Storage Cells in MTL (I.sup.2) Technology" granted May 18, 1982 to H. H. Heimeier et al
FIGS. 1, 2 and 3 respectively disclose known circuitry and structure.
FIG. 1 shows a schematic diagram of a portion of a large scale integrated (LSI) circuit structure which contains an array of I.sup.2 L cells 1, each bounded by isolation regions 2. A sectional view along line A-A is included as part of FIG. 1. The equivalent circuit of one of the cells is shown in FIG. 2. Briefly, layer 3 of highly doped N.sup.+ type material provides the substrate for the LSI structure. Each cell 1 is provided by a layer N1 of N.sup.- type material epitaxially grown in the N.sup.+ substrate 3. Regions P1 and P2 of P type material are diffused into the layer N1 and several, in this case four, regions N2.1, N2.2, N2.3 and N2.4 of N.sup.+ type material are diffused into the region P2. A diffusion of highly doped N.sup.+ type material through the body of the cell into the underlying substrate 3 provides the ladder-like isolation structure 2 effectively isolating one cell from its neighbors.
This cell structure provides a lateral semiconductor sequence P1/N1/P2 merged with a vertical semiconductor sequence N2/P2/N1. A silicon dioxide protection layer 4 overlays the surface of the LSI and is provided with apertures through which connections can be made to the two P type diffusions P1 and P2 and the four N type diffusions N2.1, N2.2, N2.3 and N2.4.
The equivalent circuit of the basic cell is shown in FIG. 2 with appropriate potentials applied so that it functions as an I.sup.2 L four output gate. In this configuration, the lateral injector PNP transistor T1 supplies injector current I.sub.J to the four-collector vertical inverting NPN multiple transistor T2. The input to the gate is applied via input conductor 5 connected to the P2 region and the outputs taken from any or all of the four collector electrodes of the multiple transistor T2 via output conductors 6.1, 6.2, 6.3 and 6.4 connected respectively to the N2.1, N2.2, N2.3 and N2.4 regions.
In operation, an effective short circuit at the input conductor 5, for example from the low level output (0.1 volts) of a preceding gate, causes the injector current I.sub.J through injector transistor T1 to be diverted to ground. The multiple electrode inverting transistor T2 consequently remains OFF and the potential on the output conductors (assuming that they are connected to appropriate loads) remain high (0.7 volts if connected as input to a succeeding gate). An effective open circuit at the input terminal 5, for example from the high level output (0.7 volts ) of a preceding gate, diverts the injector current I.sub.J through injector transistor T1 into the base region of the inverter transistor T2 causing it to conduct. Consequently, the potential on the output conductors drop to the low level (0.1 volts if the loads are provided by further identical gates).
This is the normal operation of I.sup.2 L devices, with the output collectors being pulled from some voltage, generally the device Vbe, to ground, or vice-versa. Combinations of such gates are interconnected to provide logic functions at an output node in known manner. A difficulty with I.sup.2 L circuits is that the inverting devices have a low breakdown voltage and thus cannot be used directly to drive other circuits which operate at comparatively higher voltages. There is a need therefore for an output circuit which is operable to supply the necessary current to an output node of an I.sup.2 L circuit combination in order to generate an output signal indicative of the logic condition of the output node.
A typical circuit which converts internal (on chip) I.sup.2 L signal levels to external signal levels such as VTL is shown included as part of the circuit in FIG. 3. In the figure a number of I.sup.2 L logic blocks 7 are shown connected to an output node 8. In order to interrogate the logic condition of the I.sup.2 L combination a current I.sub.D is required to be supplied to output node 8 being of a value close to that of the internal injection current I.sub.J of an I.sup.2 L gate. Depending upon the logic state of the I.sup.2 L combination, this current I.sub.D will either be diverted to ground, in which case output transistor T.sub.3 with its base connected to node 8 will remain or be turned OFF, or alternatively diverted into the base of transistor T.sub.3 in which case the transistor T3 will remain or be turned ON. The output transistor is a real on-chip transistor (i.e. not inverted) with a high beta and high collector/base, collector/emitter breakdown voltage. An output terminal 9 is connected to the collector of transistor T3 which may be operating from a relatively high supply voltage such as, in the case of VTL, 5 volts.
This prior art circuit incorporates an I.sup.2 L gate 10 comprising injector transistor T4 and multicollector inverting transistor T5 arrangement as described previously with reference to FIG. 2. The gate 10 is not standard in that is has been modified by the provision of an additional connection shorting the base of the inverting transistor T5 to its collectors.
There is no input connection to the gate which as a result of the modification functions as a rudimentary current mirror and approximately mirrors the injector current I.sub.J supplied by injector transistor T4 into the collectors of the inverting transistor T5. This current is further mirrored by conventional current mirror combination of transistors T6, T7 and T8 to provide the interrogation current I.sub.D at node 8.
In practice, this circuit has several disadvantages which lead to a poorly defined current I.sub.D. First the NPN transistors comprising the inverting combination in the I.sup.2 L gate providing the mirror function have very poor matching characteristics. The I.sup.2 L gate has a large base drive current to the merged NPN transistors which is NPN Beta inverse dependent. The PNP current mirror has collector voltages that are different and referenced to different power supplies. Thus the V.sub.ce for transistor T6 is 2V.sub.be 's whereas the V.sub.ce for transistor T8 is the supply V--V.sub.be where V is the supply voltage. As the collector slope resistance of PNP transistors in typical technologies is low and temperature dependent, this reduces the accuracy of definition of the current I.sub.D. In practice with this circuit, the cumulative effect of these three disadvantages results in the value of I.sub.D being about 30% less than the value of the injector current I.sub.J. Finally, referencing to different power supplies reduces noise immunity of the circuit which is an additional disadvantage.